View SY89844U10_5526603.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

sy89844u precision lvds runt pulse eliminator 2:1 mux with 1:2 fanout and internal termination may 2 007 m9999 -0 52207 -b hbwhelp@micrel.com or (408) 955 - 1690 precision edge is a registered trademark of micrel, inc. general description the sy89844u is a low jitter lvds, 2:1 input multiplexer (mux) optimized for r e dundant source switchover applications. unlike standard mult i plexers, the sy89844u unique 2:1 runt pulse eliminator (rpe) mux pr e vents any short cycles or ?runt? pulses during switchover. in a d dition, a unique fail - safe input protection prevents metastable conditions when the s e lected input clock fails to a dc voltage (voltage between the pins of the differential input drops below 100mv). the differential in put includes micrel?s unique, 3 - pin i n put termination architecture that allows customers to inte r face to any differential signal (ac - or dc - coupled) as small as 100mv (200mv pp ) without any level shifting or termin a tion resistor networks in the signal path. the ou t puts are 325mv lvds with fast rise/fall times guaranteed to be less than 150ps. the sy89844u operates from a 2.5v 5% supply and is guaranteed over the full industrial temper a ture range of ? 40c to +85c. the sy89844u is part of micrel?s high - speed , precision edge ? product line. all su p port documentation can be found on m i crel?s web site at: www.micrel.com . precision edge ? features ? selects between two sources, and provides a glitch - free, stable lvds outpu t ? guaranteed ac performance over temperature and supply voltage: ? wide operating frequency: 1khz to >1.5ghz ? <870ps in - to - out t pd ? <150ps t r /t f ? unique patent - pending input isolation design minimizes crosstalk ? fail - safe input prevents oscillations ? ultra - low jitter design: ? <1ps rms random jitter ? <1ps rms cycle - to - cycle jitter ? <10ps pp total jitter (clock) ? <0.7ps rms mux crosstalk induced jitter ? unique patent - pending input termination and vt pin accepts dc - and ac - coupled inputs (cml, pecl, lvds) ? 325mv lvds output swing ? 2.5v + 5% power supply ? ? 40c to +85c industrial temperature range ? available in 24 - pin (4mm x 4mm) qfn package applications ? redundant clock switchover ? fail - safe clock protection markets ? lan/wan ? enterprise servers ? ate ? test and measurement
micrel, inc. sy89844u may 2007 m9999 - 052207-b hbwhelp@micrel.com or (408) 955 - 1690 2 typical application simplified example illustrating runt pulse eliminator (rpe) when primary clock fails
micrel, inc. sy89844u may 2007 m9999 - 052207-b hbwhelp@micrel.com or (408) 955 - 1690 3 ordering information (1) part number package type operating range package marking lead finish sy89844umg qfn -24 indu s trial 844 u with pb - free bar - line indicator nipdau pb - free sy89844umgtr (2) qfn -24 indu s trial 844u with pb - free bar - line indicator nipdau pb - free notes: 1. contact factory for die availability. dice are guaranteed at t a = 25c, dc electricals only. 2. tape and reel . pin configuration 24- pin qfn
micrel, inc. sy89844u may 2007 m9999 - 052207-b hbwhelp@micrel.com or (408) 955 - 1690 4 pin description pin number pin name pin function 5, 2 23, 20 in0, /in0, in1, /in1 differential inputs: these input pairs are the differential signal inputs to the device. these inputs accept ac - or dc - coupled signals as small as 100mv (200mvpp). each pin of a pair internally terminates to a vt pin through 50 ?. please refer to the ?input interface applications? section for more details. 3, 21 vref - ac0 vref - ac1 reference voltage: these outputs bias to v cc ? 1.2v. they are used for ac - coupling inputs in and /in. connect vref - ac directly to the cor responding vt pin. bypass with 0.01 f low esr capacitor to vcc. maximum sink/source current is 1.5ma. due to the limited drive capability, the vref - ac pin is only intended to drive its respective vt pin. please refer to the ?input interface applications? section for more details. 4, 22 vt0, vt1 input termination center - tap: each side of the differential input pair terminates to a vt pin. the vt0 and vt1 pins provide a center - tap to a termination network for maximum interface flexibility. please refer to t he ?input interface applications? section for more details. 1, 6, 9, 10, 13, 19, 24 vcc positive power supply: bypass with 0.1 f//0.01 f low esr capacitors as close to the vcc pins as possible. 7, 8 11, 12 q0, /q0 q1, /q1 differential outputs: these lvd s differential output pairs are a logic function of the in0, in1, and sel inputs. please refer to the ?truth table? section below for details. 15 sel this single - ended ttl/cmos - compatible input selects the inputs to the multiplexer. note that this input i s internally connected to a 25k ? pull - up resistor and will default to logic high state if left open. 14, 17, 18 gnd exposed pad ground: ground and exposed pad must be connected to the same ground plane. 16 cap power - on reset (por) initialization capacito r. when using the multiplexer with rpe capability, this pin is tied to a capacitor to vcc. the purpose is to ensure the internal rpe logic starts up in a known state. see ?power - on reset (por) description? section for more d e tails regarding capacitor selec tion. if this pin is tied directly to vcc, the rpe function will be disabled and the multiplexer will function as a normal multiplexer. the cap pin should never be left open. truth table inputs outputs in0 /in0 in1 /in1 sel q /q 0 1 x x 0 0 1 1 0 x x 0 1 0 x x 0 1 1 0 1 x x 1 0 1 1 0
micrel, inc. sy89844u may 2007 m9999 - 052207-b hbwhelp@micrel.com or (408) 955 - 1690 5 absolute maximum ratings (1) supply voltage (v cc ) .......................... ? 0.5v to +4.0v input voltage (v in ) .................................. ? 0.5v to v cc input current source or sink current on in, /in .............. 50ma termination current source or sink current on v t .................. 100ma v ref-ac source or sink current ........................... 2ma lead temperature (soldering, 20 sec.) .......... +260c storage temperature (t s ) .................. ? 65c to 150c operating ratings (2) supply voltage (v cc ) .................. +2.375v to +2.625v ambient temperature (t a ) ................ ? 40c to +85c package thermal resistance (3) qfn ( ja ) still - air ..................................................... 50c/w qfn ( jb ) junction - to - board .................................... 30c/w dc electrical characteristics (4) t a = ? 40c to +85c, unless otherwise stated. symbol parameter condition min typ max units v cc power supply 2.375 2.5 2.625 v i cc power supply current no loa d, max v cc 105 140 ma r in input resistance (in -to -v t ) 45 50 55 ? r diff_in differential input resistance (in -to - /in) 90 100 110 ? v ih input high voltage (in, /in) 1.2 v cc v v il input low voltage (in, /in) 0 v ih ? 0.1 v v in input voltage swing (in, /in) see figure 1a. note 5. 0.1 v cc v v diff_in differential input voltage swing |in - /in| see figure 1b. 0.2 v v in_fsi input voltage threshold that triggers fsi 30 100 mv v t_in in -to -v t (in, /in) 1.28 v v ref - ac output reference voltage v cc ? 1.3 v cc ? 1.2 v cc ? 1.1 v notes: 1. permanent device damage may occur if absolute maximum ratings are exceeded. this is a stress rating only and fun c tional operation is not implied at conditions other than those detailed in the operational sections of this data sheet. exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2. the data sheet limits are not guaranteed if the device is operated beyond the operating ratings. 3. package thermal resistance assumes exposed pad is soldered (or equivalent) to the devices most negative potential on the pcb. ja and jb values are determined for a 4 - layer board in still air unless otherwise stated. 4. the circuit is designed to meet the dc specifications shown in the above table after thermal equilibrium has been established . 5. v in (max) is specified when v t i s floating.
micrel, inc. sy89844u may 2007 m9999 - 052207-b hbwhelp@micrel.com or (408) 955 - 1690 6 lvds outputs dc electrical characteristics (6) v cc = 2.5v 5%; r l = 100 ? across output pair or equivalent; t a = ? 40c to + 85c, unless otherwise stated. symbol parameter condition min typ max units v ocm output common mode voltage 1.125 1.27 5 v v o cm change in vocm between complementing output states -50 + 50 mv v out output voltage swing see figure 1a. 250 325 mv v diff - out differential output voltage swing see figure 1b. 500 650 mv lvttl/cmos dc electrical characteristics (6) v cc = 2.5 v 5%; t a = ? 40c to + 85c, unless otherwise stated. symbol parameter condition min typ max units v ih input high voltage 2.0 v v il input low voltage 0.8 v i ih input high current -125 30 a i il input low current -300 a note: 6. the circuit is designed to meet the dc specifications shown in the above table after thermal equilibrium has been established.
micrel, inc. sy89844u may 2007 m9999 - 052207-b hbwhelp@micrel.com or (408) 955 - 1690 7 ac electrical characteristics (7) v cc = 2.5v 5%; r l = 100 ? across output pair or equivalent; t a = ? 40c to + 85c, unless otherwise stated. symbol parameter condition min typ max units f max maximum operating frequency v out 200mv 1.5 2.0 ghz t pd differential propagation delay v in = 100mv to 200mv (8, 9 ) 470 625 870 ps in -to -q in -to -q v in = 200mv to 800mv (8, 9) 440 575 800 ps sel -to -q rpe enabled, see timing diagram 17 cycles sel -to -q rpe disabled (v sel = v cc /2) 550 900 ps t pd tempco differential propagation delay te m perature coeffi cient 451 fs/ o c t skew output -to - output skew note 10 5 20 ps part -to - part skew note 11 200 ps t jitter random jitter note 12 1 ps rms cycle -to - cycle jitter note 13 1 ps rms total jitter (tj) note 14 10 ps pp crosstalk - induced jitter note 15 0.7 ps rms t r, t f output rise/fall time (20% to 80%) at full output swing. 30 80 150 ps notes: 7. high - frequency ac - parameters are guaranteed by design and characterization. 8. propagation delay is a function of rise and fall time at in. see ?typic al operating characteristics? for more details. 9. propagation delay is measured with input t r , t f 300ps (20% to 80%) and v il 800mv. 10. output - to - output skew is measured between two different outputs under identical transitions. 11. part - to - part skew is defined for two parts with identical power supply voltages at the same temperature and with no skew of the edges at the respective inputs. 12. random jitter is measured with a k28.7 character pattern, measured at micrel, inc. sy89844u may 2007 m9999 - 052207-b hbwhelp@micrel.com or (408) 955 - 1690 8 functional description rpe mux and fail - safe input the sy89844u is optimized for clock switchover applications whe re switching from one clock to a n other clock without runt pulses (short cycles) is r e quired. it features two unique circuits: runt - pulse eliminator (rpe) circuit the rpe mux provides a ?glitchless? switchover between two clocks and prevents any runt pulses from occurring during the switchover transition. the design of both clock inputs is identical (i.e., the switchover sequence and protection is symmetrical for both input pair, in0 or in1. thus, either input pair may be defined as the primary input). if no t r e quired, the rpe function can be permanently di s abled to allow the switchover between inputs to o c cur immediately. if the cap pin is tied directly to vcc, the rpe function will be disabled and the multiplexer will function as a normal multiplexer. fail - safe input (fsi) circuit the fsi function provides protection against a selected input pair that drops below the minimum amplitude requirement. if the s e lected input pair drops sufficiently below the 100mv minimum si n gle - ended input amplitude limit (v in ), or 200mv di f ferentially (v diff_in ), the output will latch to the last valid clock state. rpe and fsi functionality the basic operation of the rpe mux and fsi functionality is described with the following four case descriptions. all descriptions are rel ated to the true inputs and outputs. the primary (or selected) clock is called clk1; the secondary (or alternate) clock is called clk2. due to the totally asynchr o nous relation of the in and sel signals and an a d ditional internal prote c tion against metasta bility, the number of pulses required for the operations d e scribed in cases 1 - 4 can vary within certain li m its. refer to ?timing di a grams? section for detailed inform a tion. case #1: two normal clocks and rpe enabled in this case, the frequency difference between the two running clocks, in0 and in1, must not be greater than 1.5:1. for example, if the in0 clock is 500mhz, the in1 clock must be within the range of 334mhz to 750mhz. if the sel input changes state to select the a l ternate clock, the switchover from clk1 to clk2 will occur in three stages. ? stage 1: the output will continue to follow clk1 for a limited number of pulses. ? stage 2: the output will remain low for a limited number of pulses of clk2. ? stage 3: the output follows clk2. timing dia gram 1
micrel, inc. sy89844u may 2007 m9999 - 052207-b hbwhelp@micrel.com or (408) 955 - 1690 9 case #2: input clock failure: switching from a s e lected clock stuck high to a valid clock (rpe e n abled). if clk1 fails high before the rpe mux selects clk2 (using the sel pin), the switchover will occur in three stages. ? stage 1: the output w ill remain high for a lim ited number of pulses of clk2. ? stage 2: the output will switch to low and then remain low for a limited number of fa l ling edges of clk2. ? stage 3: the output will follow clk2. timing diagram 2 note: output show s extended clock cycle during switchover. pulse width for both high and low of this cycle will always be greater than 50% of the clk2 period.
micrel, inc. sy89844u may 2007 m9999 - 052207-b hbwhelp@micrel.com or (408) 955 - 1690 10 case #3: input clock failure: switching from a selected clock stuck low to a valid clock (rpe enabled). if clk1 fails low before the rpe mux selects clk2 (using the sel pin), the switchover will occur in two stages. ? stage 1: the output will remain low for a limited number of falling edges of clk2. ? stage 2: the output will follow clk2. timing diagram 3
micrel, inc. sy89844u may 2007 m9999 - 052207-b hbwhelp@micrel.com or (408) 955 - 1690 11 case #4: i nput clock failure: switching from the selected clock input stuck in an undetermined state to a valid clock input (rpe enabled). if clk1 fails to an undetermined state (e.g., amplitude falls below the 100mv (v in ) minimum single - ended input limit, or 200mv differentially) before the rpe mux selects clk2 (using the sel pin), the switchover to the valid clock clk2 will occur either following case #2 or case #3, depending upon the last valid state at the clk1. if the selected input clock fails to a floating, static, or extremely low signal swing, including 0mv, the fsi function will eliminate any metastable condition and guarantee a stable output signal. no ringing and no undetermined state will occur at the output under these conditions. please note that the fsi function will not prevent duty cycle distortions or runt pulses in case of a slowly deteriorating (but still toggling) input signal. due to the fsi function, the propagation delay will depend on rise and fall time of the input signal and on its amplitu de. refer to ?typical operating characteristics? for detailed information. timing diagram 4
micrel, inc. sy89844u may 2007 m9999 - 052207-b hbwhelp@micrel.com or (408) 955 - 1690 12 power - on reset (por) description the sy89844u includes an internal power - on r e set (por) function to ensure the rpe logic starts - up in a known logic state once the power - supply voltage is stable. an external capacitor co n nected between v cc and the cap pin (pin 16) co n trols the delay for the power - on reset function. the required capac i tor value calculation is based upon the time the system power supply needs to po wer up to a minimum of 2.3v. the time constant for the internal power - on- reset must be greater than the time required for the power supply to ramp up to a minimum of 2.3v. the following formula describes this relationship: c( f) t dps (m s) 12(ms / f) as an example, if the time req uired for the system power supply to power up past 2.3v is 12ms, then the r e quired capacitor value on pin 16 would be: c( f) 12 ms 12 (m s / f) c 1 f
micrel, inc. sy89844u may 2007 m9999 - 052207-b hbwhelp@micrel.com or (408) 955 - 1690 13 typical operating characteristics v cc = 2.5v, gnd = 0v, t r /t f 300ps, r l = 100 ? across output pair or equivalent; t a = 25c, unless otherwise stated.
micrel, inc. sy89844u may 2007 m9999 - 052207-b hbwhelp@micrel.com or (408) 955 - 1690 14 functional characteristics v cc = 2.5v, gnd = 0v, v in 400mv pk , t r /t f 300ps, r l = 100 ? across output pair or equivalent; t a = 25c, unless otherwise s tated.
micrel, inc. sy89844u may 2007 m9999 - 052207-b hbwhelp@micrel.com or (408) 955 - 1690 15 single- ended and differential swings figure 1a. single - ended voltage swing figure 1b. differential voltage swing input stage figure 2. simplified differential input stage
micrel, inc. sy89844u may 2007 m9999 - 052207-b hbwhelp@micrel.com or (408) 955 - 1690 16 input interface applications figure 3a. lvp ecl interface (dc - coupled) figure 3b. lvpecl interface (ac - coupled) option: may connect v t to v cc figure 3c. cml interface (dc - coupled) figure 3d. cml interface (ac - coupled) figure 3e. lvds interface (dc - coupled)
micrel, inc. sy89844u may 2007 m9999 - 052207-b hbwhelp@micrel.com or (408) 955 - 1690 17 lvds output interface a pplications lvds specifies a small swing of 325mv typical, on a nominal 1.20v common mode above ground. the common mode voltage has tight limits to permit large variations in ground between an lvds driver and receiver. also, change in common mode voltage, as a function of data input, is kept to a minimum, to keep emi low. figure 4a. lvds differential measurement figure 4b. lvds common mode measurement related product and support documentation part number function data sheet link sy8 9843u precision lvpecl runt pulse eliminator 2:1 mux with 1:2 fanout and internal termination www.micrel.com/product - info/products/sy89843u.shtml. sy89845u precision cml runt pulse eliminator 2:1 mux with 1:2 fanout and internal termination www.micrel.com /product - info/products/sy89845u.shtml. hbw solutions new products and applications www.micrel.com/product - info/products/solutions.shtml
micrel, inc. sy89844u may 2007 m9999 - 052207-b hbwhelp@micrel.com or (408) 955 - 1690 18 package information 24- pin qfn pa ckages notes: 1. package meets level 2 moisture sensitivity classification. 2. all parts are dry - packed before shipment. 3. exposed pad must be soldered to a ground for proper thermal management. micrel, inc. 2180 fortune drive san jose, ca 95131 usa tel +1 (408) 944 - 0800 fax +1 (408) 474 - 1000 web http:/www. micrel.com the information furnished by micrel in this data sheet is believed to be accurate and reliable. however, no responsibility is assumed by micrel for its use. micrel reserves the right to change circuitry and specifications at any time without no tification to the customer. micrel products are not designed or authorized for use as components in life support appliances, devices or systems where mal function of a product can reasonably be expected to result in personal injury. life support devices or systems are devices or systems that (a) are intended for surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. a purchaser?s use or sale of mic rel products for use in life support appliances, devices or systems is a purchaser?s own risk and purchaser agrees to fully indemnify micrel for any damages resulting from such use or sale. ? 2005 micrel, incorporated.

▲Up To Search▲

Price & Availability of SY89844U10

	To Download SY89844U10 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .